quicksheet#2 the quickram? family of embedded standard products (esps) offers a unique combination of ram features that are ideal for designs with extremely high-performance ram, rom and fifo requirements. quickram devices embed up to 25,344 bits of sram in an array of configurable logic, enabling ram and rom functions to run at speeds over 200mhz and fifos to run at speeds of over 160mhz. the highly flexible 1152-bit ram blocks can be configured in any one of four modes and can easily be cascaded to produce greater memory widths or depths. the quicklogic development tools supporting the quickram family include a "ram wizard" intuitive graphical user interface to further simplify the design process. quickram family highlights ? h h i i g g h h p p e e r r f f o o r r m m a a n n c c e e 160mhz fifos, 200mhz rom functions, 5 ns access times, 300mhz counters ? e e m m b b e e d d d d e e d d r r a a m m multiple dual-port ram modules (up to 25,344 bits) ? c c o o n n f f i i g g u u r r a a b b l l e e four modes (64x18, 128x9, 256x4, or 512x2) ? s s y y n n c c h h r r o o n n o o u u s s / / a a s s y y n n c c h h r r o o n n o o u u s s o o p p e e r r a a t t i i o o n n supports fifo/ram/rom functions ? h h i i g g h h d d e e n n s s i i t t y y up to 90,000 usable gates, 316 i/os, eight clock networks quickram esp family dual-port embedded ram for extremely high performance functions quickram esp family device ram ram usable logic max. packages supply bits blocks gates cells i/os voltage QL4009 9,216 8 9k 160 82 68-plcc, 84-plcc, 100-tqfp 3.3v ql4016 11,520 10 16k 320 118 84-plcc, 100-tqfp, 144-tqfp 3.3v ql4036 16,128 14 36k 672 204 144-tqfp, 208-pqfp, 256-pbga 3.3v ql4058 20,736 18 58k 1,008 252 208-pqfp, 240-pqfp, 456-pbga 3.3v ql4090 25,344 22 90k 1,584 316 208-pqfp, 240-pqfp, 456-pbga 3.3v 2/2000
quicksheet#2 www.quicklogic.com sales offices quicklogic corporation sunnyvale, ca usa (408) 990-4000 (800) 842-342 info@quicklogic.com quicklogic uk and europe sales london +44-1932-579-011 eusupport@quicklogic.com quicklogic german sales munich +49-89-930-86-1070 eusupport@quicklogic.com quicklogic asia sales hong kong +(852) 8106-9091 ho@quicklogic.com quicklogic japan sales yokohama-shi +(81) 045-470-5525 suzuki@quicklogic.com ? 2000, quicklogic corporation. all rights reserved. vialink, pasic and the quicklogic logo and name are registered trademark s and quickram is a trademark of quicklogic corporation. all other company and product names are trademarks of their respective owners. printed i n usa. pn ql1002, u1 1210jhgda extreme flexibility each quickram device has from 10 to 22 1,152 bit ram modules, for a total of 11,520 to 25,344 ram bits. separate read and write ports allow full dual-port operation and support extremely high-speed operation for dual-port functions such as fifos. using two "mode" pins, designers can configure each module into 64 (deep) x 18 (wide), 128 x 9, 256 x 4, or 512 x 2 blocks. these blocks are easily cascadable to increase their effective width or depth. the unique "by nine" architecture supports error or parity bits for bytes or words without wasting additional ram blocks. each ram module supports synchronous read and write operation, as well as asynchronous reads for rom (look-up table) functions such as fast multipliers. high performance and high density because quickram devices are built using quicklogic's unique vialink ? interconnect technology and esp architecture, they are among the largest programmable devices available. density levels range from 16,000 to 90,000 usable gates with i/os from 118 to 316 respectively. even the largest devices in the family support 64x18 fifos at speeds of over 160mhz and 16-bit counters at over 300mhz. perfect for a wide range of high- speed memory applications the high density and speed of the quickram devices make them perfect for a wide range of performance-driven applications including: ? high-speed datacom and telecom functions such as atm and sonet/sdh interfaces ? video/imaging/graphics applications including display drivers and image processing ? pci 0-wait state master/target interface and controller designs ? test equipment and high-speed data acquisition ram blocks high speed logic cells interface mode[1:0] asyncrd wa[a:0] ra[a:0] wd[w:0] rd[w:0] we re wclk rclk ram module
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